Field of the Invention
The invention lies in the integrated technology field. More specifically, the invention relates to an integrated DRAM memory module, with sense amplifiers that are each formed in the integrated module from a multiplicity of transistor structures arranged regularly in cell arrays and comprise amplification transistors for bit line signal amplification, which lie opposite one another in pairs, are structurally identical and are arranged equally spaced apart in rows, and voltage equalization transistors for voltage equalization between sense amplifier drive signals. The cell array order or structure provides for each row comprising amplification transistors situated in a structurally identical transistor environment to be interrupted in a predetermined period by voltage equalization transistors.
In an integrated memory module of this type, the amplification of the bit line signal is typically performed by four amplification transistors. In each case four amplifier transistors of adjacent sense amplifiers are arranged in a row or in strip form next to one another in the layout and thus form a regular structure. In particular, these transistors are in each case arranged such that they lie opposite one another in pairs in the rows, are formed structurally identically and are arranged uniformly spaced apart from one another in the row or in the strip. On account of the very small dimensions of the respective sense amplifier, this regular structure is a necessary prerequisite for an exact imaging of a given design geometry onto a wafer.
This regular structure of amplification transistors is interrupted in predetermined periods by a structure comprising voltage equalization transistors, which typically cooperate with one another in pairs and provide a voltage equalization between sense amplifier drive signals. On account of the interposed voltage equalization transistors, in the region of these transistors, the extremely uniform geometry of the amplification transistors arranged in rows is interrupted. The consequence of this is that the amplification transistors adjoining the voltage equalization transistors find a different proximity in their position opposite the voltage equalization transistors than in their position opposite the adjoining amplification transistors of the respective row. Typically, the distance between the voltage equalization transistors and the amplification transistors in a row is also different from the distance between the amplification transistors where no voltage equalization transistors are present. In other words, in the repeated pattern of the amplification transistors arranged in rows, a gap arises where the voltage equalization transistors are located. For the exposure of the wafer, this means, as a result of the absent proximity, the structure changes with the aid of the corresponding mask, which can lead to undesired structural effects.
It is accordingly an object of the invention to provide an integrated DRAM memory component, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and in which the proximity of the amplification transistors to every location of the transistor rows is identical.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated DRAM memory module, comprising:
a plurality of sense amplifiers each formed from a multiplicity of transistor structures arranged in rows and comprising amplification transistors for bit line signal amplification, the amplification transistors lying opposite one another in pairs, being structurally identical, and arranged uniformly spaced apart in the row;
voltage equalization transistors for voltage equalization between sense amplifier drive signals disposed to interrupt a respective row formed with amplification transistors situated in a structurally identical transistor environment;
the voltage equalization transistors having a structure in a region of proximity to respectively adjoining the amplification transistors identical to a structure of the adjoining the amplification transistors; and
the voltage equalization transistors being spaced from the adjoining amplification transistors at a spacing distance equal a spacing distance between the amplification transistors of the row.
In accordance with an added feature of the invention, facing edges of mutually adjacent amplification transistors and voltage equalization transistors are formed with an identical contour.
In accordance with a concomitant feature of the invention, there is provided a dummy structure interrupting the row formed of amplification transistors situated in a structurally identical transistor environment. The dummy structure in the region of proximity to the adjoining amplification transistors is adapted identically to a structure thereof, and the dummy structure is spaced a distance from the mutually adjoining amplification transistors that equals a spacing distance between the amplification transistors of the row.
In other words, the invention accordingly provides, for the integrated DRAM memory module under discussion, that in an integrated DRAM memory module, with sense amplifiers which are each formed, in the context of the integrated module, from a multiplicity of transistor structures arranged regularly in cell arrays and comprise amplification transistors for bit line signal amplification, which lie opposite one another in pairs, are structurally identical and are arranged equally spaced apart in rows, and voltage equalization transistors for voltage equalization between sense amplifier drive signals (NCS, PCS), the cell array ordering providing for each row comprising amplification transistors situated in a structurally identical transistor environment to be interrupted in a predetermined period by voltage equalization transistors, characterized in that the structure of the voltage equalization transistors in the region of proximity to the adjoining amplification transistors is adapted to the structure thereof, and in that the voltage equalization transistors to be at the same distance from the mutually adjoining amplification transistors as the amplification transistors of the same row are from one another.
Accordingly, the invention provides identical proximities for all of the amplification transistors by virtue of the fact that the same structure or the same layout is allocated to the voltage equalization transistors adjoining the adjacent amplification transistors, and also by virtue of the fact that the distance between voltage equalization transistors and adjoining amplification transistors is made the same, primarily identical to the distances between the amplification transistors within a row.
Merely by way of example this means that, when the edges of the adjoining amplification transistors facing the voltage equalization transistors have an L shape, the same L shape is mirrored at the edges of the voltage equalization transistors, and that these L-shaped proximity structures are at the same distance as in the proximity structures within the row of adjoining amplification transistors.
The expressions xe2x80x9cidentical layoutxe2x80x9d or xe2x80x9cidentical structurexe2x80x9d or xe2x80x9cidentical structural edgesxe2x80x9d of the transistors, as used throughout this text, are to be understood as layout identities between the transistor constituents, for example the gates thereof.
In a generalized manner, the invention provides identical proximities for all of the amplification transistors in a row of amplification transistors of the sense amplifiers of the integrated DRAM memory module under discussion, to be precise including at the locations where this identical proximity is disturbed or interrupted in the DRAM memory modules according to the prior art, namely where there are regions of other proximity structures, in particular in the form of voltage equalization transistors.
However, this also applies to those structural disturbance regions which have another function, such as dummy structures for instance. In this case, too, the invention is employed and provides for identical amplification transistor environments by virtue of the fact that the respective dummy structure in the region of proximity to the adjoining amplification transistors is adapted to the structure thereof, and that the dummy structure is at the same distance from the mutually adjoining amplification transistors as the amplification transistors of the same row are from one another. In this case, the dummy structure in the region of proximity to the adjoining amplification transistors is preferably identical to the structure or edge contour thereof.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated DRAM memory module, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.